Nonvolatile memory devices such as Electrically programmable Read Only Memories ("EPROMs"), Electrically Erasable Programmable Read Only Memories ("EEPROMs"), and flash EEPROMs include an array of nonvolatile memory cells and supporting circuitry for accessing the array. A nonvolatile memory cell typically behaves like a field effect transistor and includes a select or control gate that controls the reading and writing of data to the memory cell and a floating gate that traps charge corresponding to data stored by the memory cell.
An attractive feature of nonvolatile semiconductor memories is their ability to store analog data. This permits storage of multiple bits of data in a single memory cell. As charge is added to the floating gate of a memory cell, the threshold voltage Vt of the memory cell increases, and the memory cell drain current ID ("cell current") decreases. The memory cell threshold voltage Vt is related to the memory cell drain current ID such that ID is proportional to: EQU Gm.times.(VG-Vt) for VD&gt;VG-Vt
where Gm is the transconductance of the memory cell; VG is the memory cell gate voltage; VD is the memory cell drain voltage; and Vt is the memory cell threshold voltage.
For memory cells storing multiple bits of data, each of the possible patterns of bits represents one state. In effect, the cell is storing base S data, where S is the number of states the cell is capable of storing. The bit pattern results from decoding the state data of one or multiple cells. For example, for memory cells storing two bits of data there are four bit patterns: 00, 01, 10, and 11. Each of these bit patterns is represented by a state. The particular state represented by a particular pattern of bits depends upon the type of coding used (e.g., Gray coding or binary). The type of coding generally does not effect the method of programming.
States may be defined in a variety of ways. They may be defined in terms of a range of threshold voltages Vt, a range of drain currents ID, or a range of charge. To distinguish between possible states, the states are separated by separation ranges. When a flash cell is read, the current conducted, or voltage generated, by the addressed flash cell is compared against a reference current conducted, or reference voltage generated, by a reference flash cell. The reference flash cell has a reference threshold voltage, reference drain current, or reference amount of charge in the separation range between the states such that a comparator such as a sense amplifier can determine the state of the selected flash cell.
FIG. 1 shows a conventional memory device 100 including flash memory cells 102 and 104 that are two flash cells in a flash memory array. Each flash cell includes a select or control gate coupled to word line 118, a floating gate for storing data or charge, a drain terminal coupled to transistor 110 or 112, and a source terminal coupled to ground. Flash cells 102 and 104 are uniquely addressable such that when an address is supplied to circuit 100, row and column decoding logic select flash cell 102 or 104 by applying the appropriate voltages to word line 118 and column lines COL0 and COL1.
When one of the flash cells is selected for reading, a biasing voltage is applied to word line 118. The same biasing voltage is also supplied to the select gate of reference flash cell 106. The amount of current flowing through the selected flash cell causes a voltage to develop on bit line 120. This voltage is provided to input 114 of sense amplifier 108. The voltage on input 114 may be compared with the voltage developed on input 116 by the current flowing through flash reference cell 106. The speed at which the voltages can be developed at the inputs of sense amplifier 108 has a direct impact on the overall read access time for memory device 100.
FIG. 2 shows voltages supplied to inputs 114 and 116 as a function of time when flash memory cells 102 and 104 store different states and are consecutively addressed. In this example, flash cell 102 has a lower threshold voltage than flash cell 104, and reference cell 106 has a threshold voltage in a separation range between the threshold voltages of flash cells 102 and 104. At time t0, flash cell 102 is selected by COL0 and word line 118. As flash cell 102 has a lower threshold voltage than reference cell 106, the voltage on bit line 120 and input 114 will rise to a voltage greater than input 116 at time t1. When flash cell 104 is subsequently addressed by COL1 and word line 118, flash cell 104 discharges bit line 120 and input 114 to voltage level below input 116 (e.g., at time t2). It generally requires a longer time for flash cell 104 to discharge bit line 120 from time t1 to t2, than for flash cell 102 to charge bit line 120 because of the reduced amount of current drive supplied by flash cell 104 relative to the resistance of the column load circuits. Thus, the read access time for memory device 100 may be pushed out when switching between flash cells 102 and 104.
The problem highlighted in FIG. 2 may be more acute in multi-level flash cell devices. For example, FIG. 3 shows voltages supplied to inputs 114 and 116 when flash memory cells 102 and 104 store one of four different states (i.e., two bits of data) and are consecutively addressed. In this example, flash cell 102 stores the lowest threshold voltage and flash cell 104 may store one of three higher threshold voltages corresponding to curves 130, 132, and 134. Reference cell 106 would typically be replaced by three reference cells each having a threshold voltage in separation ranges between the four states that can be stored by flash cells 102 and 104, and each resulting in voltage curves REF1, REF2, and REF3 at the input(s) of one or more sense amplifiers. As shown in FIG. 3, the higher the threshold voltage of flash cell 104, the longer it generally requires for flash cell 104 to discharge bit line 120. Thus, the read access time may be at its worst case condition when flash cell 102 stores a state corresponding to the lowest threshold voltage and flash cell 104 stores a state corresponding to a higher threshold voltage just below REF1 (i.e., curve 130).
The read access time may be further increased by the physical location of flash cells 102 and 104 within the flash memory array relative to sense amplifier 108. For example, assume that flash cells 102 and 104 are physically located at opposite ends of a long flash memory array having word line 118 and bit line 120 running substantially the entire length of the array, and sense amplifier 108 located at the end of the array nearest flash cell 104. If flash cell 102 has a lower threshold voltage than reference cell 106, then it generally requires a relatively long amount of time for the load on flash cell 102 to charge input 114 to a voltage above the voltage on input 116 because of the resistance and capacitance of bit line 120. This is generally referred to a long "bit line turn on time." This will generally push out the read access time. Additionally, when flash cell 104 is addressed, it generally takes a long time for the voltage on word line 118 to traverse the memory array and select flash cell 104. Thus flash cell 104 may have a long "word line turn on time" which generally pushes out the read access time. If, as shown in FIG. 2, flash cell 102 had a lower threshold voltage than flash cell 104, then addressing flash cell 104 after addressing flash cell 102 would also push out the read access time because it would take a relatively long amount of time for flash cell 102 to discharge the entire length of bit line 120.
The relationship of bit line turn on time, word line turn on time, and the voltages developed at inputs 114 and 116 of sense amplifier 108 is generally shown in the graph of FIG. 4. The Y axis is labeled as "Cross Time" and refers to the amount of time in FIG. 2, for example, that is required for flash cell 104 to discharge bit line 120 to a point where the voltage at input 114 crosses the voltage on input 116 (i.e., at time t2 of FIG. 2). The X axis is label ".DELTA. Turn On Time" and refers to the difference in the word line turn on time and the bit line turn on time (i.e., word line turn on time minus bit line turn on time). As shown in FIG. 4, there is a point Z at which the .DELTA. turn on time yields the fastest cross time, that is, at point at which the memory device has the fastest read access path when switching addressed flash cells that store different states. It is generally desirable to have memory device 100 operate near point Z to achieve the fastest read access time.
One previous technique used to reduce the read access time caused by switching between flash cells storing different states has been to electrically connect inputs 114 and 116 together for a period of time while charging or discharging bit line 120. However, this technique generally requires complex circuitry to control the timing of the electrical connection and requires a large amount of silicon area to implement the circuitry. This technique has also been shown to cause the input voltage to react unpredictably when the electrical connection is disconnected. In flash memory devices using multi-level cell technology, it is not obvious to which flash reference cell an addressed flash cell should be electrically connected to during the charging or discharging time. Selection of the incorrect reference cell could further increase, rather than reduce, the read access time.